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Code: Select all

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
    signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cmux3: std_logic_vector (31 downto 0);
    signal cmux4: std_logic_vector (31 downto 0);
    signal cmux5: std_logic_vector (31 downto 0);
    signal cmux6: std_logic_vector (31 downto 0);
    signal cmux7: std_logic_vector (31 downto 0);
    signal cmux8: std_logic_vector (31 downto 0);
    signal cmux9: std_logic_vector (31 downto 0);
    signal cmux10: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
    signal d: std_logic_vector (31 downto 0);
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
    mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
    mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
    mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);


    mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
    mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
    mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);

    mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
    mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);

    x1 <= not z1 and z2;
    x2 <= not z3 and z4;
    x3 <= not z7 and z6;
    x4 <= not z11 and z12;
    x5 <= not x8 and x10;
    x6 <= not x9 and x5;
    x7 <= not x1 and x2;
    x8 <= not x3 and x4;
    x9 <= not x5 and x6;
    x10 <= not x7 and x8;
    x11 <= not x9 and x10;

    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
    div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
    nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
    sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
    srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
    mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
    slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);

        -- z    s3s2s1s0
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

    z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
    z4 <= (not s (3) and not s (2) and not s (1) and s (0));
    z1 <= (not s (3) and not s (2) and s (1) and not s (0));
    z7 <= (not s (3) and not s (2) and s (1) and s (0));
    z12 <= (not s (3) and s (2) and not s (1) and not s (0));
    z6 <= (not s (3) and s (2) and not s (1) and s (0));
    z2 <= (not s (3) and s (2) and s (1) and not s (0));
    z8 <= (not s (3) and s (2) and s (1) and s (0));
    z9 <= (s (3) and not s (2) and not s (1) and not s (0));
    z10 <= (s (3) and not s (2) and not s (1) and s (0));
    z11 <= (s (3) and not s (2) and s (1) and not s (0));
    z5 <= (s (3) and s (2) and s (1) and s (0));

    sadd <= '0';
    c <= d;
    nul <= d (31);
    testnull: FOR i IN 30 DOWNTO 0 GENERATE
        nul <= d (i) nor nul;
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;


    entity opdecode is
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0)
    );
    end;

    architecture behaviour of opdecode is
        signal x0: std_logic;
        signal x1: std_logic;
        signal x2: std_logic;
    begin
        --  addi
        --  001000 rs rt imm
        --  op5 op4 op3 op2 op1 op0
        --  0   0   1   0   0   0
        --  x0: nothing
        --  x1: addi
        --  x0 <= '0'
        --  x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
        --  memtoreg <= x0 or ...;
        --  memwrite <= x0 or ...;
        --  branch <= x0 or ...;
        --  ...
        --  (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate

        x0 <= '0';
        x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
        x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
        memtoreg <= x0;
        memwrite <= x0;
        branch <= x0;
        alusrc <= x0 or x1;
        regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
        regwrite <= x0 or x1 or x2;

        -- aluop
        -- 00 -- add
        -- 01 -- sub
        -- 10 -- nutze das func feld
        -- 11

        -- x1 x2    alup
        -- 0  0     xx
        -- 0  1     0
        -- 1  0     0
        -- 1  1     0

        aluop (1) <= not (x2 or x1);
        aluop (0) <= not (x2 or x1);
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (3 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
        signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
    begin

        -- 00 add
        -- 01 sub
        -- 10 nutze das func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- add
        x0 <= '0';

        -- x1 : add
        -- x2 : sub
        -- x3 : and
        -- x4 : or
        -- x5 : nor
        -- x6 : slt
        -- x7 : xor
        -- x8 : sll
        -- x9 : srl
        -- x10: sra
        -- x11: mult
        -- x12: div

        -- aluop: 10 ...
        -- ... func:
        -- 100 000 - add 4 0
        -- 100 010 - sub 4 2
        -- 100 100 - and 4 4
        -- 100 101 - or  4 5
        -- 100 111 - nor 4 7
        -- 101 010 - slt 5 2
        -- 100 110 - xor 4 6
        -- 000 000 - sll 0 0
        -- 000 011 - sra 0 3
        -- 000 010 - srl 0 2
        -- 011 000 - mult 3 0
        -- 011 010 - div 3 2


        x1 <= (not aluop (1) and not aluop (0)) or
                (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
        x2 <= (not aluop (1) and aluop (0)) or
                (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
        x3 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
        x4 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
        x5 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
        x6 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
        x7 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
        x8 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
        x9 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
        x10 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
        x11 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
        x12 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div

        -- also
        --  a1  a0      ao2     ao1     ao0
        --  0   0       0       1       0
        --  0   1       1       1       0
        -- ... func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- vier bit
        -- 0010 - add
        -- 0110 - sub
        -- 0000 - and
        -- 0001 - or
        -- 1111 - slt

        -- selber erweitert:
        -- x
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

        aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
        aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
        aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
        aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;

    end;

Code: Select all

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component xor32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
     component nor32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component sll32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
     component srl32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;

    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
    signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cmux3: std_logic_vector (31 downto 0);
    signal cmux4: std_logic_vector (31 downto 0);
    signal cmux5: std_logic_vector (31 downto 0);
    signal cmux6: std_logic_vector (31 downto 0);
    signal cmux7: std_logic_vector (31 downto 0);
    signal cmux8: std_logic_vector (31 downto 0);
    signal cmux9: std_logic_vector (31 downto 0);
    signal cmux10: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
    signal d: std_logic_vector (31 downto 0);
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
    mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
    mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
    mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);


    mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
    mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
    mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);

    mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
    mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);

    x1 <= not z1 and z2;
    x2 <= not z3 and z4;
    x3 <= not z7 and z6;
    x4 <= not z11 and z12;
    x5 <= not x8 and x10;
    x6 <= not x9 and x5;
    x7 <= not x1 and x2;
    x8 <= not x3 and x4;
    x9 <= not x5 and x6;
    x10 <= not x7 and x8;
    x11 <= not x9 and x10;

    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
    div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
    nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
    sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
    srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
    mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
    slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);

        -- z    s3s2s1s0
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

    z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
    z4 <= (not s (3) and not s (2) and not s (1) and s (0));
    z1 <= (not s (3) and not s (2) and s (1) and not s (0));
    z7 <= (not s (3) and not s (2) and s (1) and s (0));
    z12 <= (not s (3) and s (2) and not s (1) and not s (0));
    z6 <= (not s (3) and s (2) and not s (1) and s (0));
    z2 <= (not s (3) and s (2) and s (1) and not s (0));
    z8 <= (not s (3) and s (2) and s (1) and s (0));
    z9 <= (s (3) and not s (2) and not s (1) and not s (0));
    z10 <= (s (3) and not s (2) and not s (1) and s (0));
    z11 <= (s (3) and not s (2) and s (1) and not s (0));
    z5 <= (s (3) and s (2) and s (1) and s (0));

    sadd <= '0';
    c <= d;
    nul <= d (31);
    testnull: FOR i IN 30 DOWNTO 0 GENERATE
        nul <= d (i) nor nul;
    END GENERATE;
end;

Code: Select all

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (3 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
        signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
    begin

        -- 00 add
        -- 01 sub
        -- 10 nutze das func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- add
        x0 <= '0';

        -- x1 : add
        -- x2 : sub
        -- x3 : and
        -- x4 : or
        -- x5 : nor
        -- x6 : slt
        -- x7 : xor
        -- x8 : sll
        -- x9 : srl
        -- x10: sra
        -- x11: mult
        -- x12: div

        -- aluop: 10 ...
        -- ... func:
        -- 100 000 - add 4 0
        -- 100 010 - sub 4 2
        -- 100 100 - and 4 4
        -- 100 101 - or  4 5
        -- 100 111 - nor 4 7
        -- 101 010 - slt 5 2
        -- 100 110 - xor 4 6
        -- 000 000 - sll 0 0
        -- 000 011 - sra 0 3
        -- 000 010 - srl 0 2
        -- 011 000 - mult 3 0
        -- 011 010 - div 3 2


        x1 <= (not aluop (1) and not aluop (0)) or
                (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
        x2 <= (not aluop (1) and aluop (0)) or
                (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
        x3 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
        x4 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
        x5 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
        x6 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
        x7 <= (alup (1) and not alup (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
        x8 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
        x9 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
        x10 <= (alup (1) and not alup (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
        x11 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
        x12 <= (alup (1) and not alup (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div

        -- also
        --  a1  a0      ao2     ao1     ao0
        --  0   0       0       1       0
        --  0   1       1       1       0
        -- ... func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- vier bit
        -- 0010 - add
        -- 0110 - sub
        -- 0000 - and
        -- 0001 - or
        -- 1111 - slt

        -- selber erweitert:
        -- x
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

        aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
        aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
        aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
        aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;

    end;

Code: Select all

entity ALU is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0);
    s: in std_logic_vector (3 downto 0);
    t: out std_logic;
    nul: inout std_logic;
    globalcarryflag: out std_logic
);
end;

architecture behaviour of ALU is
    component ripplecarrychainadder32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        s: in std_logic;
        t: out std_logic
    );
    end component;
    component sub32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0);
        t: out std_logic
    );
    end component;
    component and32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component or32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component xor32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
     component nor32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component sll32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component srl32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component sra32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component slt32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component mult32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;
    component div32
    port (
        a: in std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        c: out std_logic_vector (31 downto 0)
    );
    end component;

    component MUX32_2_1
    port (
        c: out std_logic_vector (31 downto 0);
        b: in std_logic_vector (31 downto 0);
        a: in std_logic_vector (31 downto 0);
        x: in std_logic
    );
    end component;
    signal z11, z10, z9, z8, z7, z6, z5, z4, z3, z2, z1, z12: std_logic;
    signal x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1: std_logic;
    signal csub: std_logic_vector (31 downto 0);
    signal cor: std_logic_vector (31 downto 0);
    signal cmux1: std_logic_vector (31 downto 0);
    signal cmux2: std_logic_vector (31 downto 0);
    signal cmux3: std_logic_vector (31 downto 0);
    signal cmux4: std_logic_vector (31 downto 0);
    signal cmux5: std_logic_vector (31 downto 0);
    signal cmux6: std_logic_vector (31 downto 0);
    signal cmux7: std_logic_vector (31 downto 0);
    signal cmux8: std_logic_vector (31 downto 0);
    signal cmux9: std_logic_vector (31 downto 0);
    signal cmux10: std_logic_vector (31 downto 0);
    signal cadd: std_logic_vector (31 downto 0);
    signal cand:  std_logic_vector (31 downto 0);
    signal cmult:  std_logic_vector (31 downto 0);
    signal cdiv:  std_logic_vector (31 downto 0);
    signal csll:  std_logic_vector (31 downto 0);
    signal csrl:  std_logic_vector (31 downto 0);
    signal csra:  std_logic_vector (31 downto 0);
    signal cslt:  std_logic_vector (31 downto 0);
    signal cxor:  std_logic_vector (31 downto 0);
    signal cnor:  std_logic_vector (31 downto 0);
    signal sadd: std_logic;
    signal d: std_logic_vector (31 downto 0);
begin
    -- 010 add
    -- 110 sub
    -- 000 and
    -- 001 or
    -- 111 slt set less than
    mux1: MUX32_2_1 PORT MAP (a=>cadd, b=>csub, c=>cmux1, x=>x1);
    mux2: MUX32_2_1 PORT MAP (a=>cand, b=>cor, c=>cmux2, x=>x2);
    mux3: MUX32_2_1 PORT MAP (a=>cxor, b=>cnor, c=>cmux3, x=>x3);
    mux4: MUX32_2_1 PORT MAP (a=>cmult, b=>cdiv, c=> cmux4, x=>x4);
    mux5: MUX32_2_1 PORT MAP (a=>csll, b=>csrl, c=>cmux5, x=>x5);
    mux6: MUX32_2_1 PORT MAP (a=>csra, b=>cslt, c=>cmux6, x=>x6);


    mux7: MUX32_2_1 PORT MAP (a=>cmux1, b=>cmux2, c=>cmux7, x=>x7);
    mux8: MUX32_2_1 PORT MAP (a=>cmux3, b=>cmux4, c=>cmux8, x=>x8);
    mux9: MUX32_2_1 PORT MAP (a=>cmux5, b=>cmux6, c=>cmux9, x=>x9);

    mux10: MUX32_2_1 PORT MAP (a=>cmux7, b=>cmux8, c=>cmux10, x=>x10);
    mux11: MUX32_2_1 PORT MAP (a=>cmux9, b=>cmux10, c=>d, x=>x11);

    x1 <= not z1 and z2;
    x2 <= not z3 and z4;
    x3 <= not z7 and z6;
    x4 <= not z11 and z12;
    x5 <= not x8 and x10;
    x6 <= not x9 and x5;
    x7 <= not x1 and x2;
    x8 <= not x3 and x4;
    x9 <= not x5 and x6;
    x10 <= not x7 and x8;
    x11 <= not x9 and x10;

    and1: and32 PORT MAP (a=>a, b=>b, c=>cand);
    or1: or32 PORT MAP (a=>a, b=>b, c=>cor);
    add1: ripplecarrychainadder32 PORT MAP (a=>a, b=>b, s=>sadd, t=>globalcarryflag, c=>cadd);
    xor1: xor32 PORT MAP (a=>a, b=>b, c=>cor);
    div1: div32 PORT MAP (a=>a, b=>b, c=>cdiv);
    nor1: xor32 PORT MAP (a=>a, b=>b, c=>cnor);
    sub1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csub);
    sll1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csll);
    sra1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csra);
    srl1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>csrl);
    mult1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cmult);
    slt1: sub32 PORT MAP (a=>a, b=>b, t=>globalcarryflag, c=>cslt);

        -- z    s3s2s1s0
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

    z3 <= (not s (3) and not s (2) and not s (1) and not s (0));
    z4 <= (not s (3) and not s (2) and not s (1) and s (0));
    z1 <= (not s (3) and not s (2) and s (1) and not s (0));
    z7 <= (not s (3) and not s (2) and s (1) and s (0));
    z12 <= (not s (3) and s (2) and not s (1) and not s (0));
    z6 <= (not s (3) and s (2) and not s (1) and s (0));
    z2 <= (not s (3) and s (2) and s (1) and not s (0));
    z8 <= (not s (3) and s (2) and s (1) and s (0));
    z9 <= (s (3) and not s (2) and not s (1) and not s (0));
    z10 <= (s (3) and not s (2) and not s (1) and s (0));
    z11 <= (s (3) and not s (2) and s (1) and not s (0));
    z5 <= (s (3) and s (2) and s (1) and s (0));

    sadd <= '0';
    c <= d;
    nul <= d (31);
    testnull: FOR i IN 30 DOWNTO 0 GENERATE
        nul <= d (i) nor nul;
    END GENERATE;
end;

Code: Select all

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (3 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
        signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
    begin

        -- 00 add
        -- 01 sub
        -- 10 nutze das func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- add
        x0 <= '0';

        -- x1 : add
        -- x2 : sub
        -- x3 : and
        -- x4 : or
        -- x5 : nor
        -- x6 : slt
        -- x7 : xor
        -- x8 : sll
        -- x9 : srl
        -- x10: sra
        -- x11: mult
        -- x12: div

        -- aluop: 10 ...
        -- ... func:
        -- 100 000 - add 4 0
        -- 100 010 - sub 4 2
        -- 100 100 - and 4 4
        -- 100 101 - or  4 5
        -- 100 111 - nor 4 7
        -- 101 010 - slt 5 2
        -- 100 110 - xor 4 6
        -- 000 000 - sll 0 0
        -- 000 011 - sra 0 3
        -- 000 010 - srl 0 2
        -- 011 000 - mult 3 0
        -- 011 010 - div 3 2


        x1 <= (not aluop (1) and not aluop (0)) or
                (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
        x2 <= (not aluop (1) and aluop (0)) or
                (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
        x3 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
        x4 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
        x5 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
        x6 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
        x7 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
        x8 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
        x9 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
        x10 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
        x11 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
        x12 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div

        -- also
        --  a1  a0      ao2     ao1     ao0
        --  0   0       0       1       0
        --  0   1       1       1       0
        -- ... func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- vier bit
        -- 0010 - add
        -- 0110 - sub
        -- 0000 - and
        -- 0001 - or
        -- 1111 - slt

        -- selber erweitert:
        -- x
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

        aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
        aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
        aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
        aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;

    end;

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity or32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of or32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) or a (i);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity nor32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of nor32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) nor a (i);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity xor32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of xor32 is
begin
    genor32: FOR i IN 31 DOWNTO 0 GENERATE
        c (i) <= b (i) xor a (i);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity sll32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of sll32 is
begin
    genor32: FOR i IN 30 DOWNTO 0 GENERATE
        c (i) <= a (i+1);
    END GENERATE;
end;

library ieee;
use ieee.std_logic_1164.all;

entity srl32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of srl32 is
begin
    genor32: FOR i IN 31 DOWNTO 1 GENERATE
        c (i) <= a (i-1);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity slt32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of slt32 is
-- not implemented yet
begin
    genor32: FOR i IN 31 DOWNTO 1 GENERATE
        c (i) <= a (i-1);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity sra32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of sra32 is
-- not implemented yet
begin
    genor32: FOR i IN 31 DOWNTO 1 GENERATE
        c (i) <= a (i-1);
    END GENERATE;
end;


library ieee;
use ieee.std_logic_1164.all;

entity mult32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of mult32 is
-- not implemented yet, comes soon
begin
    genor32: FOR i IN 31 DOWNTO 1 GENERATE
        c (i) <= a (i-1);
    END GENERATE;
end;



library ieee;
use ieee.std_logic_1164.all;

entity div32 is
port (
    a: in std_logic_vector (31 downto 0);
    b: in std_logic_vector (31 downto 0);
    c: out std_logic_vector (31 downto 0)
);
end;

architecture behaviour of div32 is
-- not implemented yet
begin
    genor32: FOR i IN 31 DOWNTO 1 GENERATE
        c (i) <= a (i-1);
    END GENERATE;
end;

Code: Select all

library ieee;
use ieee.std_logic_1164.all;


    entity opdecode is
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0)
    );
    end;

    architecture behaviour of opdecode is
        signal x0: std_logic;
        signal x1: std_logic;
        signal x2: std_logic;
    begin
        --  addi
        --  001000 rs rt imm
        --  op5 op4 op3 op2 op1 op0
        --  0   0   1   0   0   0
        --  x0: nothing
        --  x1: addi
        --  x0 <= '0'
        --  x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
        --  memtoreg <= x0 or ...;
        --  memwrite <= x0 or ...;
        --  branch <= x0 or ...;
        --  ...
        --  (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate

        x0 <= '0';
        x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
        x2 <= not opcode (5) and not opcode (4) and not opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);
        --  gehoert in funktionsdekodierer
        -- x2, 1 alle opcode 0
        -- opcode, func feld
        -- 00 000, 100 000 - add
        -- 00 100, xxx xxx - addi
        -- 00 000, 100 100 - and
        -- 00 000, 100 111 - nor
        -- 00 000, 100 101 - or
        -- 00 000, 101 010 - slt
        -- 00 000, 101 011 - sub
        -- 00 000, 100 110 - xor
        -- 00 000, 000 000 - sll
        -- 00 000, 000 010 - srl
        -- 00 000, 000 011 - sra
        -- 00 000, 011 010 - div
        -- 00 000, 011 000 - mult

        --  gehoert in funktionsdekodierer
        -- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
        -- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
        -- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
        -- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
        -- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
        -- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
        -- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
        -- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
        -- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
        -- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
        -- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
        -- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult


        memtoreg <= x0;
        memwrite <= x0;
        branch <= x0;
        alusrc <= x0 or x1;
        regdst <= x0 or not x1; ---? Bei immidiate - 15:15 - ist aber x1
        regwrite <= x0 or x1 or x2;

        -- aluop
        -- 00 -- add
        -- 01 -- sub
        -- 10 -- nutze das func feld
        -- 11

        -- aluop    x
        -- 0  0     - (0)
        -- 0  1     1
        -- 1  0     2
        -- x  x     -

        aluop (1) <= x0 or x1;
        aluop (0) <= x0 or x2;
    end;

library ieee;
use ieee.std_logic_1164.all;


    entity funcdecode is
    port (
        aluop: in std_logic_vector (1 downto 0);
        func: in std_logic_vector (5 downto 0);
        aluoperation: out std_logic_vector (3 downto 0)
    );
    end;

    architecture behaviour of funcdecode is
        signal x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12: std_logic;
    begin

        -- 00 add
        -- 01 sub
        -- 10 nutze das func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- add
        x0 <= '0';

        -- x1 : add
        -- x2 : sub
        -- x3 : and
        -- x4 : or
        -- x5 : nor
        -- x6 : slt
        -- x7 : xor
        -- x8 : sll
        -- x9 : srl
        -- x10: sra
        -- x11: mult
        -- x12: div

        -- aluop: 10 ...
        -- ... func:
        -- 100 000 - add 4 0
        -- 100 010 - sub 4 2
        -- 100 100 - and 4 4
        -- 100 101 - or  4 5
        -- 100 111 - nor 4 7
        -- 101 010 - slt 5 2
        -- 100 110 - xor 4 6
        -- 000 000 - sll 0 0
        -- 000 011 - sra 0 3
        -- 000 010 - srl 0 2
        -- 011 000 - mult 3 0
        -- 011 010 - div 3 2


        x1 <= (not aluop (1) and not aluop (0)) or
                (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- add
        x2 <= (not aluop (1) and aluop (0)) or
                (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- sub
        x3 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0)); -- and
        x4 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0)); -- or
        x5 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- slt
        x6 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0)); -- nor
        x7 <= (aluop (1) and not aluop (0) and func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0)); -- xor
        x8 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0)); -- sll
        x9 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0)); -- sra
        x10 <= (aluop (1) and not aluop (0) and not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0)); -- srl
        x11 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0)); -- mult
        x12 <= (aluop (1) and not aluop (0) and not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0)); -- div

        -- x2, 1 alle opcode 0
        -- opcode, func feld
        -- 00 000, 100 000 - add
        -- 00 100, xxx xxx - addi
        -- 00 000, 100 100 - and
        -- 00 000, 100 111 - nor
        -- 00 000, 100 101 - or
        -- 00 000, 101 010 - slt
        -- 00 000, 101 011 - sub
        -- 00 000, 100 110 - xor
        -- 00 000, 000 000 - sll
        -- 00 000, 000 010 - srl
        -- 00 000, 000 011 - sra
        -- 00 000, 011 010 - div
        -- 00 000, 011 000 - mult

        --  gehoert in funktionsdekodierer
        -- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
        -- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
        -- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
        -- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
        -- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
        -- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
        -- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
        -- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
        -- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
        -- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
        -- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
        -- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult

        -- also
        --  a1  a0      ao2     ao1     ao0
        --  0   0       0       1       0
        --  0   1       1       1       0
        -- ... func feld

        -- 010 - add
        -- 110 - sub
        -- 000 - and
        -- 001 - or
        -- 111 - slt

        -- vier bit
        -- 0010 - add
        -- 0110 - sub
        -- 0000 - and
        -- 0001 - or
        -- 1111 - slt

        -- selber erweitert:
        -- x
        -- 3    0 0 0 0     and
        -- 4    0 0 0 1     or
        -- 1    0 0 1 0     add
        -- 7    0 0 1 1     xor
        -- 12   0 1 0 0     div
        -- 6    0 1 0 1     nor
        -- 2    0 1 1 0     sub
        -- 8    0 1 1 1     sll
        -- 9    1 0 0 0     sra
        -- 10   1 0 0 1     srl
        -- 11   1 0 1 0     mult
        -- 5    1 1 1 1     slt

        aluoperation (3) <= x0 or x9 or x10 or x11 or x5;
        aluoperation (2) <= x0 or x12 or x6 or x2 or x8 or x5;
        aluoperation (1) <= x0 or x1 or x7 or x2 or x8 or x11 or x5;
        aluoperation (0) <= x0 or x4 or x7 or x6 or x8 or x10 or x5;

    end;

Code: Select all

-- mit store - word - kurze pause

    entity opdecode is
    port (
        opcode: in std_logic_vector (5 downto 0);
        memtoreg: out std_logic;
        memwrite: out std_logic;
        branch: out std_logic;
        alusrc: out std_logic;
        regdst: out std_logic;
        regwrite: out std_logic;
        aluop: out std_logic_vector (1 downto 0)
    );
    end;

    architecture behaviour of opdecode is
        signal x0: std_logic;
        signal x1: std_logic;
        signal x2: std_logic;
    begin
        --  addi
        --  001000 rs rt imm
        --  op5 op4 op3 op2 op1 op0
        --  0   0   1   0   0   0
        --  x0: nothing
        --  x1: addi
        --  x0 <= '0'
        --  x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0)
        --  memtoreg <= x0 or ...;
        --  memwrite <= x0 or ...;
        --  branch <= x0 or ...;
        --  ...
        --  (regdst: Bit 20 bis 16) immdiate - rs, rt, rd oder rs, rd/tr immidiate

        x0 <= '0';
        x1 <= not opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);

        --  gehoert in funktionsdekodierer
        -- x2, 1 alle opcode 0
        -- opcode, func feld
        -- 00 000, 100 000 - add
        -- 00 100, xxx xxx - addi
        -- 00 000, 100 100 - and
        -- 00 000, 100 111 - nor
        -- 00 000, 100 101 - or
        -- 00 000, 101 010 - slt
        -- 00 000, 101 011 - sub
        -- 00 000, 100 110 - xor
        -- 00 000, 000 000 - sll
        -- 00 000, 000 010 - srl
        -- 00 000, 000 011 - sra
        -- 00 000, 011 010 - div
        -- 00 000, 011 000 - mult

        --  gehoert in funktionsdekodierer
        -- y1 <= func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- add
        -- y2 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and not func (0); -- and
        -- y3 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and func (0); -- nor
        -- y4 <= func (5) and not func (4) and not func (3) and func (2) and not func (1) and func (0); -- or
        -- y5 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slt
        -- y6 <= func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sub
        -- y7 <= func (5) and not func (4) and not func (3) and func (2) and func (1) and not func (0); -- xor
        -- y8 <= not func (5) and not func (4) and not func (3) and not func (2) and not func (1) and not func (0); -- sll
        -- y9 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and not func (0); -- slr
        -- y10 <= not func (5) and not func (4) and not func (3) and not func (2) and func (1) and func (0); -- sra
        -- y11 <= not func (5) and func (4) and func (3) and not func (2) and func (1) and not func (0); -- div
        -- y12 <= not func (5) and func (4) and func (3) and not func (2) and not func (1) and not func (0); -- mult

        memtoreg <= x0 and (not x1 or not x2);
        memwrite <= x0 and (not x1 or x2);
        branch <= x0 and (not x1 or not x2);
        alusrc <= x0 or (not x1 or x2); -- weil 0 +4
        regdst <= x0 or (not x1 or x2); ---? Bei immidiate - 15:15 - ist aber x1
        regwrite <= x0 or (x1 or not x2);

        -- LOAD WORD

        -- STORE WORD
        -- MUX 1 - HIGH - ALUSrc
        -- MUX 2 - MemToReg - LOW
        -- WE - Datenspeicher - MemWrite - HIGH
        -- WE - Registersatz - Regwrite - LOW
        -- MUX 3 - Achtung - LOW - 20:16 von oben her gesehen, also LOw
        -- MUX 4 - Branch LOW

        x2 <= opcode (5) and not opcode (4) and opcode (3) and not opcode (2) and not opcode (1) and not opcode (0);

        -- aluop
        -- 00 -- add
        -- 01 -- sub
        -- 10 -- nutze das func feld
        -- 11

        -- aluop    x
        -- 0  0     - (0)
        -- 0  1     1
        -- 1  0     2
        -- x  x     -

        aluop (1) <= x0 or x1;
        aluop (0) <= x0 or x2;
    end;